TSMC builds 0.42nm interface to improve next-gen MoS2 transistors

TSMC, in collaboration with researchers from Taiwan’s National Yang Ming Chiao Tung University (NYCU), has developed a novel interface design for next-generation transistors based on molybdenum disulfide (MoS2). The breakthrough, detailed in a study published in Nature Electronics, introduces a 0.42-nanometer buffer layer that enhances the performance of ultra-thin transistors. This advancement aims to overcome long-standing challenges in creating reliable, high-performance transistors using atomically thin materials. The research team engineered the atomic boundary between the semiconductor and the insulating layer, a critical factor in determining the efficiency and functionality of transistors. Traditionally, improving transistor performance has centered on developing better semiconductor materials. However, this study highlights the importance of refining the interface itself. By modifying the interaction between the materials, the researchers achieved improved electrical control and reduced resistance to electron flow. At the heart of the innovation is the use of monolayer MoS2, a material just one atom thick yet capable of exhibiting useful electrical properties. To address the limitations of existing fabrication techniques, the team employed an ultrathin epitaxial aluminium layer, which was subsequently oxidized to form a 0.42-nanometer aluminium oxide buffer. This layer served as a mediator between the MoS2 and the high-κ hafnium oxide gate dielectric. The result was a smoother, more uniform surface that minimized electrical interference and enhanced overall device performance. One of the key challenges in working with atomically thin semiconductors is the lack of dangling bonds on their surfaces. This characteristic complicates the growth of a uniform dielectric layer, often leading to gaps and defects that degrade performance. The researchers tackled this issue by introducing the aluminium oxide buffer, which effectively mitigated these structural imperfections. As a consequence, the resulting transistors demonstrated higher carrier mobility, meaning electrons moved more freely through the material, while maintaining strong electrostatic control. The study underscores the significance of interface engineering in advancing two-dimensional (2D) electronics. For years, much of the focus in semiconductor research has been on discovering superior materials. However, this work suggests that optimizing the boundaries between materials can yield equally transformative results. “Our research shows that the atomic interface between materials can be just as important,” explained Professor Wen-Hao Chang, the study’s corresponding author from NYCU. He emphasized that by carefully designing the interface, the team managed to eliminate a key limitation that had hindered the progress of 2D transistors. The technique described in the study is particularly relevant for large-scale production processes such as chemical vapor deposition (CVD), which is used to fabricate thin films over extensive areas. Achieving consistent quality and performance across such scales has been a persistent hurdle. The introduction of the 0.42-nanometer buffer layer offers a promising solution, enabling the scalable manufacturing of high-performance transistors based on MoS2. Looking ahead, the success of this interface design could pave the way for more compact, energy-efficient electronic devices. With its potential to enable smaller, faster, and more power-efficient transistors, this development marks a crucial step forward in the evolution of semiconductor technology. Researchers and industry leaders will likely continue exploring ways to refine and apply this approach to real-world applications.