More compact computer chips: the transistor conquers the third dimension

A breakthrough in semiconductor technology has been achieved with the development of a new computer chip featuring transistors that measure just 0.7 nanometers in size, roughly equivalent to seven hydrogen atoms. This innovation, led by researchers at IBM’s research center in Albany, New York, marks a major leap forward in miniaturization, allowing for up to 100 billion transistors to fit on a chip the size of a postage stamp. The achievement challenges previous physical limits and opens new possibilities for advanced computing applications. The progress follows decades of relentless miniaturization driven by Moore's Law, which predicted that the number of transistors on a chip would double approximately every two years. Initially formulated by Intel co-founder Gordon Moore in 1965, this principle has guided the evolution of microprocessors. In the early days, the first integrated circuit, created by Jack Kilby in 1958, contained just four transistors and measured about the size of a paperclip. By the 2000s, the smallest structures on a Pentium IV processor had shrunk to 100 nanometers. Today, modern chips feature components as small as ten nanometers, enabling around 20 billion transistors to be packed onto a fingernail-sized surface. Now, IBM’s latest design pushes these dimensions even further. Until recently, the primary method of reducing transistor size relied on using shorter wavelengths of light in photolithography processes. Extreme ultraviolet (EUV) light, with a wavelength of 13.5 nanometers, allows for the creation of features as small as about seven nanometers. However, as transistors shrink beyond this point, performance issues arise. When the conductive channel within a field-effect transistor becomes too narrow, leakage currents increase, leading to noise and potential short circuits. These problems hinder reliability and efficiency, while also contributing to higher heat generation, a challenge that becomes more pronounced as processors become more powerful. To overcome these limitations, IBM researchers have adopted a three-dimensional approach to chip architecture. Instead of arranging transistors in a flat, two-dimensional layout, they stack multiple thin layers of semiconductor material vertically. Each layer is enclosed by a gate electrode, which controls the flow of current through the transistor. This design enables better control over electrical currents, significantly reducing unwanted leakage. It also allows for a denser arrangement of transistors, increasing the number that can be placed on a given area. The individual transistors themselves are several nanometers in size, making them among the smallest ever produced. This advancement builds upon earlier work by the same team. Five years ago, IBM introduced a prototype chip using a similar stacked structure, achieving a minimum feature size of two nanometers and housing 50 billion transistors on a chip smaller than a fingernail. The recent breakthrough represents a substantial improvement, demonstrating the feasibility of pushing miniaturization further into the sub-nanometer range. As the demand for faster, more efficient computing continues to grow, particularly in fields such as artificial intelligence, robotics, and autonomous vehicles, innovations like this will play a crucial role in meeting future technological demands. The success of IBM’s new chip suggests that three-dimensional architectures could become a key strategy in overcoming the physical constraints of traditional two-dimensional designs. The next steps likely involve scaling up production and integrating these advanced chips into commercial products.